Revised 19970224

by Zac Schroff.

Some portions of this document are probably copyright Hitachi America and others. The rest is copyright 1997 Zac Schroff, all rights reserved. You may use the data presented here as you see fit. No warranties are made concerning the data or the accuracy thereof or the fitness thereof for any particular purpose or the usability thereof for any particular purpose. Please distribute this document without modifications. If you want to add your own observations or comments, please include them in another file. If you have additional information, confirmation or corrections, please send them to zschroff[-at-]docsware[-dot-]com.
Thanks!

The Psion display is memory mapped to two addresses. Reading or writing to these addresses will access certain ports, as shown below.

Note that the address counter is incremented or decremented at each read from the port at 0181.

The busy & address counter register is split into two parts. The Msb (bit 7) of the byte is the busy
flag (this flag MUST be zero when accessing the display). The other seven bits (0..6) are the
address counter within its particular space (there are two spaces: display memory and character
generator). Note that reads seem to be able to occur at any time, where writes and commands can
sometimes take up to several milliseconds before the display is ready for the next command or
write. It is not documented what overrunning the screen will do.

Commands go to control port, optional data can follow. Some commands cause the data port to do certain things, others make the data port write to the character generator or the display. Note that the cursor is always displayed at the current offset for text accesses to the data port (moving the cursor moves where these accesses will occur).

Note that when the machine is in a `powered down' state, the display hardware gets no power. Therefore, the entire display state is quite indeterminate on power up. The machine keeps track of most of the display state in scratchpad memory.
See the book review: Machine Language Programming on the Psion Organiser by Bill Aitken for information about the system's internal memory structures.

The character generator memory is documented by Psion, except for a few minor items that might prove useful with all the other data that are provided in this file. It seems that in 8-raster mode, there is enough character generator memory for eight characters. However, in 11-raster mode, there is only enough character generator memory for four characters. I have taken the 11-raster mappings straight from Hitachi's documentation, since I have not experimented with them.

Pixels are mapped 5*8 as eight rows of xxxDDDDD where xxx does not matter, and DDDDD are the displayed pixels (1 is dark (on). In 5*11 mode, the pixels are mapped as 11 rows of xxxDDDDD where xxx does not matter, and DDDDD are displayed pixels as above, followed by five bytes that do not matter (they are ignored).

The CM and XP use the following display memory layout (cursor positions in hex arranged in the order they appear on the display):

Off screen: 20..7F (seem to be arranged as additional 16-byte lines, as above).

*MY* LZ64 uses the following layout (no, it does not seem to make sense, and everybody at Psion I have mentioned this to swears I am totally out of my mind, but I have carefully verified it many many times):

The Psion start-up sequence appears to use initially:

Footnote 0 : The Psion Organiser II seems to make no allowances for this
                   feature -- hardware, firmware, or software.

Footnote 1 : The cursor is not moved unless the command indicates it is
                   moved. Some commands shift the cursor (move by one), others
                   move it directly. ALL WRITES/READS to the data port will
                   shift the cursor automatically according to the address index
                   auto-increment/decrement flag.

Footnote 2 : It is possible to have any combination of cursor modes : both
                   off (Psion uses this when no input is desired), underline on
                   (Psion uses this for numeric input), flashing box on (Psion does
                   not use this), flashing box and underline on (Psion uses this for
                   text input).

Footnote 3 : In byte mode, the data port is accessed all at once. In nibble
                   mode (byte mode clear), the data port is accessed high-nibble then
                   low-nibble. Note that BOTH nibbles are in the upper nibble of the
                   port when in nibble mode the way the Psion has the device wired.

Footnote 4 : 2-line on CM and XP. 4-line on LZ. The LZ uses an odd sort of
                   interlaced screen. I have not yet found a quite satisfactory
                   method of addressing it. I am working on it.

Footnote 5 : This can not coexist with 2-line enable on the Organiser II. It
                   appears that the 2-line enable takes priority.

Footnote 6 : Hitachi indicates all `don't care' bits should be left zero
                   for what they call `future compatibility'...

Footnote 7 : Hitachi's documentation is /very/ vague here, but a little
                  experimentation indicates that the auto-update of the LCD offset
                  is in the `right' direction for the cursor movement. If the
                  cursor is set to auto-increment, so is the display. If the
                  cursor is set to auto-decrement, so is the display. This makes
                  it easy to set up a scrolling banner on a standard Hitachi part,
                  but works out to be well nigh useless on the Psion parts.

Copyright: Hitachi America, others & copyright Zac Schroff 1997.

If you would like to contact me to ask a question, generally chat or comment about this subject, or any other aspect of programming the Psion Organiser II I would be very pleased to speak with you:

Zac Schroff
zschroff[-at-]docsware[-dot-]com

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