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Technical Reference Manual

LOW LEVEL PACK ACCESS

Although a deep understanding of the hardware of datapacks and their interface to the Organiser is useful it is not necessary. The operating system software provides all the routines necessary for accessing datapacks while hiding all their complexities from the programmer.

NAMING CONVENTIONS

HARDWARE

USAGE

ORGANISER INTERFACE

NAMING CONVENTIONS

The following conventions are used when referring to lines on the EPROM in the datapack and the external datapack connector.

  1. Lines on the EPROM are preceded by 'E'.
  2. Lines on the datapack and Organiser connectors are preceded by 'S'.
  3. Lines which are active low (inverted logic) are followed by '_B'.

Hence the chip select line on the EPROM is abbreviated ECS_B and the slot select line on the Organiser connector is abbreviated SS_B.

HARDWARE

The following is a selection of the packs available for use on the MKII Organiser:

  • 8k bytes with linear addressing
  • 16k bytes with linear addressing
  • 32k bytes with linear addressing
  • 64k bytes with 256 byte paged addressing
  • 128k bytes and more with 256 byte paged and 16k byte segment addressing

Packs above 64k are not supported in the CM version of the MKII Organiser.

The addressing modes are explained more fully below. Although the same physical connector is used to connect the different types of datapack, the way the individual lines are used varies.

A datapack consists of 2 major components, an EPROM and a counter. The EPROM is the device where the data is stored and the counter is used to select where in the EPROM data is stored and retrieved.

EPROM (Erasable Programmable Read Only Memory)

EPROMs are read only memory devices but they can be written to (programmed) and erased under special circumstances. It is worth noting the following important facts about EPROMs.

  1. In a blank (erased) EPROM all the bytes are equal to $FF (all bits set).
  2. EPROMs are erased by subjecting them to ultraviolet light through the quartz window on top of the chip.
  3. Bytes are written by applying a special set of voltages and signals to the EPROM.
  4. When writing to an EPROM, bits can only be modified from a 1 to a 0.

The EPROMs used in datapacks have an 8-bit data bus. The size of their address bus varies from 13 bits for an 8K EPROM to 16 bits for a 64K EPROM. Other lines that can be present on an EPROM are as follows:

  • Chip Select (abbreviated ECS_B): when this line is low the EPROM is active. When this line is high the EPROM will ignore any other signals present on any other lines.
  • Output Enable (abbreviated EOE_B): when this line and ECS_B are low the EPROMs outputs are active and it is possible to read from the EPROM.
  • Programming Supply Voltage (abbreviated EVPP): this line is normally at 5V but is raised to between 12V and 21V (depending on size and type of EPROM) when writing to the EPROM. On 32k and larger EPROMs, EVPP is combined with EOE_B.
  • Program (abbreviated EPGM_B): only on some EPROMs (8k,16k). It is used when writing to the EPROM. On 32k and larger EPROMs EPGM_B is combined with EOE_B.

NB. Although the names of these lines are similar to those present on the datapack connector there is not necessarily any direct connection between similarly named lines.

Reading from EPROM

In general to read from an EPROM the following procedure must be followed.

  1. Set up the required address on the EPROM
  2. Set EOE_B low
  3. Set ECS_B low
  4. Read data on the data bus
  5. Set ECS_B high
  6. Set EOE_B high

The configuration of EVPP and EPGM_B is dependent on the type of EPROM but does not change during the read cycle.

Writing to EPROM

In an erased or blank EPROM all the bytes are $FF, i.e. all bits are 1. To write to an EPROM the relevant bits are "blown" from ones to zeroes.

So to write a $3 to the EPROM a $3 is latched on the data bus and the relevant programming pulses applied to the EPROM. This causes the EPROM to AND the current contents with $3 and store the result back into the EPROM.

If the EPROM was blank then the byte blown will be ($3 AND $FF) = $3. If, however, the EPROM was not blank and, say, the byte $81 was previously stored in the EPROM then the byte blown will be ($3 AND $81) = $1.

This can be used to advantage for writing headers on packs. If a valid record header is $81 then at a later date this can be "blown" down to $1 to indicate an erased record.

The algorithm for writing to EPROMs varies depending on the type of the EPROM. The following is an example of one algorithm to write to an 8k or 16k EPROM. The algorithm used by the operating system is not described here because of its complexity in handling the many different types of EPROM.

  1. Set up the required address on the EPROM
  2. Set EOE_B high
  3. Raise EVPP to the required voltage (21V for 8k or 16k EPROM type)
  4. Latch data onto the data bus
  5. Set ECS_B low
  6. Set EPGM_B low
  7. Wait for 50 ms
  8. Set EPGM_B high
  9. Set the data bus to input
  10. Set EOE_B low
  11. Read back data and verify. If it is not the same as the programmed data then programming has failed (possibly due to non erased or faulty EPROM).
  12. Set EOE_B high
  13. Set ECS_B high
  14. Lower EVPP to 5v

ADDRESSING MODES

To address an 8k byte EPROM 13 address lines are required, while a 16k byte EPROM requires 14 a 32k byte EPROM needs 15 address lines.

Hence to connect an 8k byte EPROM to be directly addressable a 27-way connector would be required consisting of the following:

  1. 13 address lines
  2. 8 data lines
  3. 4 control lines (CS,OE,VPP,PGM)
  4. 2 power supply lines (5V and 0V)

To connect a 32k byte EPROM to be directly addressable a 28-way connector would be required consisting of the following:

  1. 15 address lines
  2. 8 data lines
  3. 3 control lines (CS,OE,VPP)
  4. 2 power supply lines (5V and 0V)
Linearly Addressed Datapacks

To cut down the size of connector and to provide a more consistent interface a counter has been connected to the address lines (A1 upwards) of the EPROM. The counter is then interfaced to via only 2 or 3 control lines (depending on the EPROM type). On an 8k datapack there are 2 control lines connected to the counter:

  1. Master Reset (abbreviated SMR). When this line is high the counters are reset. Also if the clock line is low (see below) this results in an address of zero on the EPROM.
  2. Clock (abbreviated SCLK). This line has a dual function
    • It acts as the least significant address bit (A0). If SCLK is low then the address on the EPROM will be even. If clock is high then address on the EPROM will be odd.
    • When SCLK goes from high to low the counter is incremented resulting in the address on the EPROM being incremented by 2, but since A0 will also go low and decrement the address. The result is the address on the EPROM is incremented by 1.

Thus to set the address on the EPROM to zero SCLK should be set low and MR should be pulsed high. To then set address $1 SCLK should be set high. To then set the address to $2 SCLK should be set low again, and so on. To set the address $100 on the EPROM SMR should be pulsed high and then SCLK toggled 256 times. The counter is set up to "wrap around" the size of the pack- i.e. counting to address 8192 on an 8k pack will leave it set at address 0. This sort of pack is addressed linearly and is referred to as a linearly address datapack.

Page Counted Datapacks

Obviously accessing higher addresses in the EPROM this way increases the access time. To access the last byte of a 8k datapack SCLK must be toggled 8191 times. To decrease the access time on larger packs (32k bytes and larger) a 256 byte page counter has been introduced. This line is called SPGM_B. SPGM_B is used when writing to (programming) 8k and 16k datapacks.

On these page counted packs there are 2 counters:

  1. This counter is connected to address lines A1 to A7 on the EPROM and is incremented by SCLK as described above.
  2. This counter is connected to address lines A8 to A15 (depending on the EPROM size) and is incremented by bringing SPGM_B from a high state to a low state. (Going from low to high has no effect).

Both counters are reset to zero by pulsing SMR high.

To set an address on the EPROM to $100 on a page counted pack SCLK is set low, SMR is pulsed high and then SPGM_B is pulsed high.

To access the last byte of a 32k byte datapack SPGM_B must be pulsed 127 times and then SCLK must be toggled 255 times.

Both counters on a paged pack "wrap around". The counter incremented by SCLK wraps around $100 bytes, i.e. toggling SCLK $100 times will not change the address on the EPROM. The page counter wraps around the size of the pack, i.e. pulsing SPGM_B 128 times will not change the address on a 32k EPROM.

This sort of pack is referred to as a "page counted" or "paged" pack. Both linear and paged 32k datapacks have been produced.

Segmented Datapacks

A 128k byte EPROM would normally require 17 address lines which would make it physically too large to fit inside a datapack. However a version of a 128k byte EPROM is made which consists of 8 x 16k byte segments. The EPROM is addressed as a normal 16k byte EPROM with 14 address lines. Inside the EPROM there is a segment register which you can write to via the data bus by setting up a special condition on the control lines.

To write to the segment register the EPROM must be selected and its outputs disabled. To do this, the lines SOE_B (output enable) and SS_B (slot select) must be used.

The following procedure must be followed to write to the segment register:

  1. Set SMR high
  2. Set SOE_B high
  3. Set SPGM_B Low
  4. Make sure SVPP is set to 5V
  5. Output segment number on data bus
  6. Set SS_B low
  7. Set SS_B high
  8. Set SMR low

To access the last byte of a 128k byte datapack 7 must be written to the segment register, SPGM_B must be pulsed 63 times and then SCLK must be toggled 255 times. On a 128k pack only the bottom 3 bits of the segment address are used; the top 5 bits are ignored. Writing an 8 to the segment register of a 128k EPROM datapack is the same as writing a 0.

RAMPACKS

Rampacks are packs that have RAM rather than EPROM as their storage medium. This has advantages and disadvantages:

  • RAM can be written to much faster than EPROM (the same speed as reading in fact).
  • The RAM used in rampacks is CMOS RAM and uses less power than EPROM.
  • RAM does not require 21V when writing to it and hence has lower power consumption.
  • RAM can be altered and does not require formatting with ultraviolet light.
  • RAM is volatile and requires a back up battery to retain its contents.
  • Data in RAM is not as secure as in EPROM and is more easily corrupted (e.g., by pulling rampack out of Organiser while it is being accessed).
  • RAM is much more expensive byte for byte than EPROM.
  • Rampacks contain a lithium battery that has an estimated lifetime of 5 years.

The 32k rampack is a paged datapack and has a hardware ID byte of 1.

128k datapacks also have page counters so they are "page counted, segmented packs".

All datapack handling routines in the operating system will handle 32k and 64k paged rampacks and 128k (and more) segmented paged rampacks. The CM operating system does not handle rampacks.

USAGE

8K AND 16K DATAPACKS

All 8K and 16k datapacks are linearly addressed datapacks.

The following conditions are required to access 8k and 16k datapacks:

READING

  • SCLK Don't care (either high or low)
  • SMR low
  • SVPP 5v
  • SOE_B low
  • SPGM_B high
  • SS_B low

WRITING

  • SCLK Don't care (either high or low)
  • SMR low
  • SVPP 21v
  • SOE_B high
  • SPGM_B low
  • SS_B low

32K DATAPACKS

Both linearly addressable and paged 32k datapacks are produced.

The following conditions are required to access 32k linearly addressed datapacks:

READING

  • SCLK Don't care (either high or low)
  • SMR low
  • SVPP 5v
  • SOE_B low
  • SS_B low

WRITING

  • SCLK Don't care (either high or low)
  • SMR low
  • SVPP 21v
  • SOE_B high
  • SS_B low

The following conditions are required to access 32k paged datapacks:

READING

  • SCLK Don't care (either high or low).
  • SMR low
  • SVPP 5v
  • SOE_B low
  • SS_B low

WRITING

  • SCLK Don't care
  • SMR low
  • SVPP 21v
  • SOE_B high
  • SS_B low

64K DATAPACKS

The majority of 64k datapacks produced have been paged however a small number of linearly addressed 64k packs were produced.

The following conditions are required to access 64k paged datapacks:

READING

  • SCLK Don't care
  • SPGM_B high
  • SMR low
  • SVPP 5v
  • SOE_B low
  • SS_B low

WRITING

  • SCLK Don't care
  • SPGM_B low
  • SMR low
  • SVPP 21v
  • SOE_B high
  • SS_B low

128K AND BIGGER DATAPACKS

All 128k datapacks are segmented and paged.

The following conditions are required to access 128k datapacks:

READING

  • SCLK Don't care
  • SPGM_B Don't care
  • SMR low
  • SVPP 5v
  • SOE_B low
  • SS_B low

WRITING

  • SCLK Don't care
  • SPGM_B Don't care
  • SMR low
  • SVPP 21v
  • SOE_B high
  • SS_B low

32k, 64k, 128k AND BIGGER RAMPACKS

All 32k and 64k rampacks are paged.

All 128k and bigger rampacks are segmented and paged.

The following conditions are required to access rampacks:

READING

  • SCLK Don't care
  • SPGM_B Don't care
  • SVPP Don't care (5v recommended)
  • SMR low
  • SOE_B low
  • SS_B low

WRITING

  • SCLK Don't care. (either high or low)
  • SPGM_B Don't care
  • SVPP Don't care (5V recommended)
  • SMR low
  • SOE_B high
  • SS_B low

ORGANISER INTERFACE

The Organiser has three interface slots; one top slot and two datapack slots. This section describes the two datapack slots.

The top slot is very similar to the two datapack slots but has some unique features. It is described separately in chapter External Interfacing.

ORGANISER SIDE SLOT CONNECTOR

There are sixteen lines on the Organiser side slot connector, as follows:

SD0 - SD7 Data bus
SMR Master Reset
SCLK Clock
SOE_B Output Enable
SS_B Slot Select
Gnd 0v
SPGM_B Program
SVCC 5v
SVPP Program Voltage

These are the same as the datapack connector.

PROCESSOR INTERFACE

The ports on the 6303 and the I/O addresses that are associated with the datapack interface are as follows:

  • PORT 2 (POB_PORT2, address $3, data direction register $1). This 8-bit bi-directional port is used as the data bus to all the datapack slots (including the Top slot). When no pack is plugged in this data bus will read zero. 
  • PORT 6 (POB_PORT6, address $17, data direction register $16). This 8-bit bi-directional port is used for the control lines. All lines are defined as outputs when in use and inputs when not in use. When this port is set to all inputs the slots are powered down and deselected.
    bit 0 SCLK Clock line to the datapack slots
    bit 1 SMR Master reset line
    bit 2 SPGM_B Program line
    bit 3 SOE_B Output Enable line. When this line and SS_B are low the EPROMs outputs are active and it is possible to read from the EPROM. SOE_B set high enables SVPP to be switched to 21V (see also SCA_ALARMHIGH).
    bit 4 SS1_B Chip select line for slot 1. Selects slot 1 when low.
    Bit 5 SS2_B Chip select line for slot 2. Selects slot 2 when low.
    Bit 6 SS3_B Chip select line for the top slot. Selects top slot when low.
    Bit 7 PACON_B When this line is low the slots are powered up by setting VCC to 5V. When this line is high all the slots are powered down.
  • SCA_PULSEENABLE ($200): Enables generation of 21V
  • SCA_PULSEDISABLE ($240): Disables generation of 21V
  • SCA_ALARMHIGH ($280): Enables SVPP to be switched to 21V. Also used for sound generation (key click, beep etc.).
  • SCA_ALARMLOW ($2C0): Disables SVPP being switched to 21V. Also used for sound generation with SCA_ALARMLOW.
  • PORT 5 (POB_PORT5, address $15): Only bit 1 (ACOUT) of this port is associated with the datapack interface. When this bit is high this indicates the 21V is ready to be switched on to the packs.

NB. Port 2 can also be used for serial communications. Bit 2 of this port is used for external clock input. To enable this bit to be used as an output $4 must be stored in the Rate/Mode Control Register (RMCR, address $10). If this is not done Bit 2 of port 2 will remain an input irrespective of what is in the data direction register. For further details see page 50 of Hitachi's HD6301X-HD6303X Family Users Manual. On reset zero is stored in the RMCR.

The following equalities are assumed in the machine code examples:

         SCLK           =0
         SMR            =1
         SPGM           =2
         SOE_B          =3
         SS1_B          =4
         SS2_B          =5
         SS3_B          =6
         PACON_B        =7
Powering up the Slots

The 5v supply (SVCC) and program voltage supply (SVPP) to the slots are switchable by software. These supplies are common to all the slots.

The slots are powered up by setting PACON_B low. This sets SVCC and SVPP to 5V.

After powering up the slots there should be a delay of at least 50ms to allow the power to settle. During this delay all lines of port 6, except PACON_B, should be set to inputs. The slots should be powered down whenever possible to reduce power consumption. Setting SVPP to 21V is described below.

The following example powers up the slots.

; Make port 6 an input. This powers down the slots and deselects them.
; This should have been done immediately after the slots were last used.
        CLR     POB_DDR6
;
; Make port 2 inputs. Port 2 (pack data bus) should always be left inputs.
        CLR     POB_DDR2
; Initialize port 6 so it has the correct data when it is made an output.
; Make SS1_B=SS2_B=SS3_B=1,SMR=SCLK=PACON_B=SOE_B=0,SPGM_B=1
        LDA     A,#$74
        STA     A,POB_PORT6:
; Make PACON_B of port 6 an output, powers up slots
        LDA     A,#$80
        STA     A,POB_DDR6:
; Wait for power to settle
        LDX     #11520                  ; 50 ms delay
1$:
        DEX
        BNE     1$
; Make rest of port 6 outputs now the slots are on
        LDA     A,#$FF
        STA     A,POB_DDR6:
; The slots are now powered up, but none are yet selected.
Selecting a Datapack Slot

As can been seen from the above diagram the datapack data bus (SD0-SD7 on port 2), SMR, SOE_B and SCLK (on port 6) are common to all three slots. SPGM_B is common to the two side slots. To select which slot is in use the three chip select lines (SS1_B,SS2_B,SS3_B) are used.

The chip select lines use inverse logic so when the lines are high the slot is deselected and when a line is low the slot is selected.

WARNING: Only one slot must be selected at a time. Selecting two or more slots simultaneously can result in permanent damage to the hardware!

The following rules must be adhered to when accessing the datapack slots:

  1. When not in use all slots should be left deselected and powered off where possible.
  2. When not in use the data bus (port 2) should be left defined as an input.
  3. In general, with the exception of toggling the SCLK line, all control line manipulation should be done with all slots deselected.

An example of selecting a slot is in the next section.

Reading from a Datapack Slot

If the slots have been powered up then the following program will read a byte from the datapack in slot 1 at it's current address.

; Make port2 inputs.
        CLR     POB_DDR2
; set SPGM_B high and SOE_B low
        BSET    SPGM_B,POB_PORT6:
        BCLR    SOE_B,POB_PORT6:
; select slot 1 (this is always done last)
        BCLR    SS1_B,POB_PORT6:
        LDA     B,POB_PORT2:            ; read data into B register
; deselect slot 1
        BSET    SS1_B,POB_PORT6:

NOTE: If there is no pack plugged into the current slot then there is always a zero on the data bus (all lines on the pack data bus are pulled low). This fact is used to detect if a pack is present. If the first byte of a pack is read as a zero then it is assumed there is no pack in the slot. Hence it is important to make sure the first byte of a pack is not zero.

Hardware ID Byte

On certain packs and devices there is an ID byte hardwired into the pack. This byte is read in the normal way except that SMR is held high during the read cycle. This byte does not exist on standard datapacks and attempting to read it will return the first byte on the pack. At present the only pack which has a hardware ID byte is the external rampack, which has an ID byte of 1. However no attempt should be made to read the hardware ID from the top slot.

If the slots have been powered up then the following program will read the hardwired ID byte from the datapack in slot 1.

; Make port2 inputs.
        CLR     POB_DDR2
; set SMR high
        BSET    SMR,POB_PORT6:
; set SPGM_B high and SOE_B low
        BSET    SPGM_B,POB_PORT6:
        BCLR    SOE_B,POB_PORT6:
; select slot 1
        BCLR    SS1_B,POB_PORT6:
; read hardwired ID byte into B register
        LDA     B,POB_PORT2:
; deselect slot 1
        BSET    SS1_B,POB_PORT6:
Setting the Program Voltage (SVPP)

It is not recommended that users attempt to write their own code to write to datapacks. The following information is only given for completeness. The 21V required for programming EPROMs is generated using a hardware "pump" similar to those found in electronic flash guns. After the pump is turned on you must wait for the voltage to reach the required level (like waiting for the ready light to appear on a flash gun).

The following lines are used to control SVPP:

  • PORT 6 (POB_PORT6, address $17)
    When Bit 3 of this port (SOE_B) is set high together with SCA_ALARMHIGH, 21V (if generated) is switched to SVPP.
  • Location $200 SCA_PULSEENABLE
    Enables generation of 21V (starts hardware pump)
  • Location $240 SCA_PULSEDISABLE
    Disables generation of 21V (stops hardware pump)
  • Location $280 SCA_ALARMHIGH
    Enables SVPP to be switched to 21V with SOE_B
  • Location $2C0 SCA_ALARMLOW
    Disables SVPP being switched to 21V
  • PORT 5 (POB_PORT5, address $15).
    Only one bit of this port is associated with the datapack interface:
    ACOUT- When this bit (bit 1) is high this indicates the 21V is ready to be switched on to the packs.

SCA_PULSEENABLE, SCA_PULSEDISABLE etc., are activated by accessing the relevant memory location with either a read or write. It is recommended the TST instruction is used, i.e.

        TST SCA_PULSEENABLE      ; starts hardware pump
        TST SCA_PULSEDISABLE     ; stops hardware pump

NOTE. The packs must be turned on (PACON_B low) when switching 21V to SVPP. Damage may result to the packs or Organiser if this is not done. The following sequence will switch SVPP to 21V:

  1. Set SOE_B low, TST SCA_ALARMLOW
    make sure initially switched off.
  2. TST SCA_PULSEENABLE
    start pump.
  3. Wait for ACOUT to come high-wait until voltage is high enough.
  4. TST SCA_PULSEDISABLE
    stop pump.
  5. TST SCA_ALARMHIGH and set SOE_B high
    21V is now switched to SVPP.
  6. Wait 5ms to allow the voltage to settle.

TST SCA_ALARMLOW or setting SOE_B low will switch SVPP back to 5V.

WARNING: The 21V should not be switched to SVPP while the pump is on as this can result in damage to the hardware.

After pumping, the voltage is stored in a capacitor. This means there is only a limited amount of energy available for blowing EPROMs before repumping is required. The operating system allows for 24ms of blowing time for each pump cycle. This will only be available after ACOUT goes high as the capacitor will discharge itself through leakage.

The pump charges a standard tolerance 100uF 40V electrolytic capacitor to 35V which is then regulated to 21V before being switched to SVPP.

NB.

  1. If the 21V is switched to SVPP before the ready condition is detected, or it is left switched on and not repumped, then a voltage somewhere between 5V and 21V will be switched to SVPP. This can result in a variety of disastrous effects (e.g. destruction of data) depending on the conditions under which it occurs.
  2. The operating system keyboard interrupt routine can TST SCA_ALARMHIGH under certain circumstances, so it is important that in any routine where SOE_B may be high interrupts must be disabled.
Writing to a Datapack

The EPROMs are written to using a variation of the INTEL quick pulse programming algorithm. Users are advised not to attempt to write their own EPROM programming code, but to use the supplied operating system calls.

EXAMPLE

The following code powers up the slots and then reads the first 20 bytes of a pack in slot 1. It contains no checking to see if a pack is in the slot or if it is, what sort of pack it might be.

It is recommended that the operating system be used to power up and down the slots and the second example shows how this is done. An explanation of the operating system calls is given in the next section.

 ; Save interrupt mask and disable interrupts
        TPA
        PSH     A
        SEI
; Initialise ports
; 4 must be stored in RMCR to allow bit 2 port 2 to be an output.
        LDA     A,#$4
        STA     A,POB_RMCR:
; Make port 6 an input. This powers down the slots and deselects them.
        CLR     POB_DDR6
; Make port 2 inputs. Port 2 (pack data bus) should always be left inputs.
        CLR     POB_DDR2
; Initialise port 6 so it has the correct data when it is made an output.
; Make SS1_B=SS2_B=SS3_B=1,SMR=SCLK=PACON_B=SOE_B=0,SPGM_B=1
        LDA     A,#$74
        STA     A,POB_PORT6:
; Make PACON_B of port 6 an output, powers up slots
        LDA     A,#$80
        STA     A,POB_DDR6:
; Wait for power to settle
        LDX     #11520                  ; 50 ms delay
1$:
        DEX
        BNE     1$
; Make rest of port 6 outputs now the slots are on
        LDA     A,#$FF
        STA     A,POB_DDR6:
; Reset pack counters with master reset
        BSET    SMR,POB_PORT6:          ; Master reset high
; Store 0 in segment register in case we have 128k pack
        BSET    SOE_B,POB_PORT6:
        LDA     A,#$FF
        STA     A,POB_DDR2:             ; make port 2 output
        CLR     A
        STA     A,POB_PORT2:            ; 0 on data bus
        BCLR    SPGM_B,POB_PORT6:
        BCLR    SS1_B,POB_PORT6:         ; select slot 1 and latch data
        BSET    SS1_B,POB_PORT6:         ; deselect slot
        BCLR    SOE_B,POB_PORT6:
        BCLR    SMR,POB_PORT6:          ; Master reset low
        BSET    SPGM_B,POB_PORT6:
        CLR     POB_DDR2                ; make port 2 inputs again
        BCLR    SS1_B,POB_PORT6:        ; select slot 1
        LDX     #DATA                   ; where to save data
LOOP:
        LDA     B,POB_PORT2:            ; read data
        STA     B,0,X                   ; store data
        BTGL    SCLK,POB_PORT6:         ; increment counter on EPROM
        INX
        CPX     #DATA+20                ; Have we reached the end yet ?
        BNE     LOOP                    ; If not loop
        BSET    SS1_B,POB_PORT6:         ; deselect slot
        CLR     POB_DDR6                ; Turn off all slots
        PUL     A
        TAP                             ; restore interrupt mask

The following example does the same as previous one but uses operating system calls for powering up and down the slots. If the user has to write their own pack reading routine then this is the preferred method.

; Save interrupt mask and disable interrupts
        TPA
        PSH     A
        SEI
; Initialize ports, power up, select required slot and reset pack counters
        CLR     A
        LDA     B,#PAKB
        OS      PK$SETP
        BCS     ERROR                   ; optional error checking
        LDX     #DATA                   ; where to save data
LOOP:
        LDA     B,POB_PORT2:            ; read data
        STA     B,0,X                   ; store data
        BTGL    SCLK,POB_PORT6:         ; increment counter on EPROM
        INX
        CPX     #DATA+20                ; Have we reached the end yet
        BNE     LOOP                    ; If not loop
; turn off slots
        OS      PK$PKOF
        PUL     A
        TAP                             ; restore interrupt mask


 
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