Psion Organiser II Top Slot (D) Hardware Overview.

Introduction

It is the intention of this document to give an overview of the hardware of the Organiser TOP SLOT so the reader can gain a broad understanding of its basic structure and function.

It is impossible to describe the structure of the top slot without also describing the structure of all 3 interface slots, as all are linked internally. The structure consists of an 8 bit bi-directional bus coupled with 7 control lines (3 of which are used as device selects) and two power lines. We can divide this interface into 3 separate sections of interest and discuss current drain:

A) Power related lines.
B) Data related lines.
C) Control lines.
D) Maximum Current Drain of Top Slot (D)

A) The Power Lines

The VB line (pin 11 Slot D only)

This is commonly used as the external power supply input. All the internal power lines found in the Organiser can be derived from this line. This line is isolated from the battery with a service diode. If an external supply is not used, then VB can be used as a power output.

As an output the battery voltage (minus a diode drop) will appear on this line (5.5 - 8.5 Volts dependant on battery condition).

As an input the external voltage applied should be higher than the battery to ensure no drain from the battery. However it is advised that any external power supply should also feed through a forward diode, so as to ensure no reverse current to the external source when it is powered off.

It should be noted that VB only occurs in the TOP SLOT, slots B and C have an SVPP line on pin 16, which is linked through a 21 volt regulator for use when writing to DataPaks.

The SVCC line (pin 13 in Ton slot, Pin 15 for B & C) Also called VCC3.

This is the main power supply line to the slots, and is regulated to 5 Volts (+/- 5%), it is derived from the VB rail.

The power budget allocated for each slot is 40rnA for an unselected device and 70mA for a selected device. (However in some cases such as the 128k datapak up to l00mA is allowable). As only one slot is active at a time this will give 40+40+70=150mA as a peak power drain.

SVCC is switched on and off by the PACON signal from bit 7 of processor PORT 6.

The GND line (pin 9 on Top Slot, Pin 13 on B &C)

This is the 0 Volts signal ground line.

B) The Data lines.

All of the lines that make up the data bus have their origins in port 2 of the HD6303X processor. The primary use of port 2 is as an 8 bit bi-directional data bus.

It can be controlled by 2 registers:

• Port 2 - DDR (Data Direction Register) at $0001
• Port 2 - Data register at $0003

The DDR determines which I/O direction is to be used, (0 for input, 1 for output) only 2 bits of the DDR are used

• Bit 0 - defines the I/O direction of SD0
• Bit 1 - defines the I/O direction of SD1-7

WARNING. THE DDR IS A WRITE ONLY REGISTER, NO ATTEMPT SHOULD BE MADE TO READ FROM IT.

When the Organiser is off (i.e. the processor is in standby mode) the DDR is automatically set for input. In subsequent operation this should be used as a default state, in particular the DDR should always be set to input when SVCC is turned off.

With DDR set to output, data can be set onto the bus by a write to the data register at $0003. The bus is configured as follows:

C) Control lines

The majority of these lines are controlled from the Processor port 6, which again has one data register, and one Data direction register (DDR). The Port 6 DDR is controlled in the same way as Port DDR.

The SS1.SS2 and SS3 lines (pin 12 an all slots)

These lines are defined as the slot select lines, they are controlled by bits 4,5 and 6 of Port 6 accordingly. The inactive state here is with all bits set high and thus all slots are de-selected.

Only one slot should be selected at any one time.

The AC line (pin 14 on Slot D only)

The AC signal from slot 3 can be used to allow an external device to turn the Organiser on. In order to activate this function, the AC signal should be pulled low by an external device. For instance the Comms link does this by use of an Open-collector npn transistor.

The SCK line (pin 10 on all slots)

The SMR line (pin 16 on Top slot, pin 9 an B & C)

The SPGM line (pin 14 on Slot B & C only)

The SQE line (pin 15 on Top slot, pin 11 an B & C)

These remaining control lines are general purpose, they are controlled by bits 0,1,2 and 3 of processor port 6. Their use is defined by the device that is currently selected. It should be noted that SPGM is not available on slot 3.

D) Maximum Current Drain From the Top Slot (D).

This section specifies the maximum current drain from the top slot interface. The Current figure obtained is the highest safe limit for a bar code reader or magnetic card reader to draw. This will help in selecting suitable bar coding wands, scanners, laser guns or card readers for the Organiser Interface boards.

The total maximum current that can be drawn from the Vcc3 regulator is 150mA when an external power supply of 10.5 Volts is used.

This figure has been determined so that no damage can occur to the Organiser II power supply providing this figure is not exceeded.

So in the case of third party companies or yourselves designing and developing your own interfaces, the following restrictions apply.

1. An external power supply with a maximum voltage output of 10.5 Volts at 150 mA should be used.
2. This will then permit a third slot peripheral device to draw up to a maximum of 80 mA when active and 20mA when passive.

More details on how these figures are arrived at are covered on the following pages of this document, where other top slot issues are discussed.

Top Slot (D) Index page

The information in this data sheet is accepted for use entirely at your own risk. The Psion Organiser II team will not be held responsible in any way for your use of this information.

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